With the continuous increase of the integration level of the semiconductor devices, the critical dimensions (CDs) of transistors have been continuously reduced. Reducing the CDs of the transistors means more and more transistors can be disposed in one chip; and the performance of the chip is enhanced. However, with the continuous decrease of the area of the chip, more challenges occur. With rapid size reduction of the transistor, the thickness of the dummy gate dielectric layer and the operation voltage are unable to change accordingly. Thus, it is more difficult to reduce the short channel effect. Accordingly, the leakage current in the channel of the device is increased.
To reduce the short channel effect of the semiconductor device, ultra shallow junction (USJ) technology has been developed. However, the USJ technology is easy to cause the transistor to have a junction capacitance issue and a junction leakage issue in drain region, especially for the source/drain regions of the NMOS device where precise control of the implantation parameters are needed.
The existing semiconductor structures have a large short channel effect. The disclosed methods and semiconductor structures are directed to solve one or more problems set forth above and other problems in the art.